The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
The instant invention pertains to semiconductor devices, fabrication and processing and more specifically to a static random access memory cell.
Semiconductor memories are vital components for mainframe and personal computers, telecommunications, automotive and consumer electronics, and commercial and military avionics systems. Semiconductor memories are characterized as volatile random access memories (RAMs) or nonvolatile devices. RAMs can either be static mode (SRAMs) where digital information is stored by setting the logic state of a bistable device, or dynamic mode (DRAMs) where digital information is stored through periodic charging of a capacitor. SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding functions in the chip allow access to each cell for read/write functions. SRAM memory cells use active feedback in the form of cross-coupled inverters to store a bit of information as a logical xe2x80x9c0xe2x80x9d or a logical xe2x80x9c1xe2x80x9d. The active elements in the memory cells need a constant source of power to remain latched in the desired state. The memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Address multiplexing is used to reduce the number of input and output pins. SRAMs have undergone dramatic increases in density in the past several years.
Standard SRAM memory cells have many variations. The basic CMOS SRAM cell consists of two n-channel pull-down (or xe2x80x9cdrivexe2x80x9d) transistors and two p-channel load transistors in a cross-coupled inverter configuration, with two n-channel select transistors added to make up a six-transistor cell. Polysilicon load resistors have been used instead of PMOS transistors to reduce the cell size. Furthermore, there are application-specific variations of the basic SRAM cell. Application-specific SRAMs include extra logic circuitry to make them compatible for a specific task. For instance, an eight-transistor, double-ended, dual-port cell can be accessed through both ports and is useful in cache architectures embedded in memory of a microprocessor. A nine transistor content-addressable memory cell is used in applications where both the contents and location of the cell must be known.
In each application, there is a need to not only reduce the total area needed to make an effective and reliable SRAM cell, but also to increase access speed while reducing the power consumed by the SRAM cells. Power can be reduced by lowering the supply voltage. However, both speed and stability are degraded with lower supply voltages. Hence, a need has arisen for a low power (low operating voltage) SRAM cell which has increased access speed and good stability.
An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the first transistor; and a second transistor having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the second transistor and the current path of the first transistor, the current path of the second transistor connected to the backgate/body connection of the first transistor; an input/output conductor; and a pass transistor coupling the memory cell to the input/output conductor. In an alternative embodiment, the memory cell further includes: a third transistor having a control electrode and a current path electrically connected to the current path of the first transistor and the backgate/body connection and control electrode of the second transistor, the control electrode of the third transistor electrically connected to the current path of the second transistor and the control electrode and backgate/body connection of the first transistor; and a fourth transistor having a control electrode and a current path electrically connected to the current path of the second transistor, the control electrode of the third transistor, and the backgate/body connection and the control electrode of the first transistor, the control electrode of the fourth transistor electrically connected to the current path of the first transistor, the current path of the third transistor, and the control electrode and the backgate/body connection of the second transistor. In another alternative embodiment, the backgate/body of the first transistor is electrically connected to the control electrode of the first transistor by a first diode (preferably a Schottky diode), and the backgate/body of the transistor is electrically connected to the control electrode of the second transistor by a second diode (preferably a Schottky diode).